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august 2011 doc id 17594 rev 3 1/26 AN3232 application note mounting recommendations for stac ? boltdown packages introduction rf power transistors are amongst the highest power density devices in the semiconductor industry. it is crucial to the reliability a nd performance of such devices to consider mechanical stress and thermal and electrical resistance within the application environment. the general purpose of this application note is to provide guidelines for mounting various types of stac ? packages in amplifiers or application boards (pcb) by means of bolting or by soldering. specific attention is paid to the stac244b and stac265b boltdown styles and the stac244f and stac265f flangeless styles, which are used to encapsulate numerous vdmos and ldmos technology products. this application note is intended to provide mounting tips and design guidelines. for actual data please refer to the relevant product datasheet. stac is a registered trademarks of stmicroelectronics. figure 1. stac boltdown packages www.st.com
contents AN3232 2/26 doc id 17594 rev 3 contents 1 epoxy sealed, non-herme tic rf power packages . . . . . . . . . . . . . . . . . 5 2 exceptional thermal per formance potential of the stac package concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 heatsink selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 core preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 mounting base surface conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 thermal interface material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 seating plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 printed circuit board (pcb) cons iderations . . . . . . . . . . . . . . . . . . . . . 15 9 package attachment to core by means of boltdown method . . . . . . . 16 9.1 required hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.2 considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.3 procedure summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10 package attachment to thermal base by means of solderi ng . . . . . . . 20 10.1 hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10.2 solder reflow equipment and methods . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 12 conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AN3232 list of tables doc id 17594 rev 3 3/26 list of tables table 1. preferred copper core thickness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. surface conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. common tims . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. recommended screw torque . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. pb-free process - package classification reflow temperatures . . . . . . . . . . . . . . . . . . . . . . 21 table 6. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
list of figures AN3232 4/26 doc id 17594 rev 3 list of figures figure 1. stac boltdown packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. drying times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. infrared imaging of a stac package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. pocket depth consideration (mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. lead bending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. package cut and pads layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. ideal screw-center spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. first boltdown mounting steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. seho fds ?maxipower? reflow oven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. component level temperature profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AN3232 epoxy sealed, non-hermetic rf power packages doc id 17594 rev 3 5/26 1 epoxy sealed, non-hermetic rf power packages epoxy sealed products, such as the stac package family, should be received in an n2- backfilled, vacuum-sealed esd b ag containing a desiccant. this decreases the possibility of moisture uptake by the package materials during transit and long-term storage. stac packages carry a moisture sens itivity rating of 3 (msl3), bu t have demonstrated capabilities of up to msl1. even with such shipping methods, it is advised to store epoxy sealed packages in the original containers, or in a dry box, until required for soldering. when the environmental history of devices is not well-known, such as after a prolonged storage period, it is a well- practiced safety measure to bake non-hermetic packages for 24 hrs at 125 c prior to soldering operations. these conditions can be accelerated or lengthened as a function of temperature, up to the limits imposed by shipping containers, by trays, or by device maximum ratings. refer to figure 2 for recommended baking conditions. figure 2. drying times under no circumstances should any epoxy-sealed package be treated as a hermetically sealed package, due to the fact that such sealing materials are not impervious to moisture ingress. however, it is important to point out that rf power packages are typically constructed using engineering ceramics and polymers which, on their own, demonstrate high resistance to moisture penetration, such as the proprietary liquid crystal polymer materials upon which stac packages are realized.
epoxy sealed, non-hermetic rf power packages AN3232 6/26 doc id 17594 rev 3 power rf packages typically require a reliabl e, low thermal resistance attachment to a heatsink. in this respect, nothing out-performs a direct attachment of the device flange, or thermal base, to the heatsink by means of soldering. this can be accomplished using any of the pbsn or pb-free soldering methods used throughout the electronic industry. the final soldering step may be preceded by a hot-solder dip of the package base and/or leads, as required for situations that require attention to au content of the solder joint. alternatively, the packages may be inserted into an amplifier using a pick-and-place methodology, so that complete soldering is accomplished in a single reflow. some amplifier assemblies require a manual approach for device positioning on a pcb while soldering bases to copper core heatsinks. in such manual operations stac boltdown style packages have the unique possibility of serving as a built-in clamp to accomplish both tasks expeditiously. these manual efforts are rewarded by an extremely low thermal resistance, achieved by an ultra-thin solder joint case-to-heatsink, referred to as the rth c- hs . at the same time, the need to allocate valuable amplifier real estate to specialized clamping fixtures is eliminated. the approaches to soldering rf transistors in amplifier housings are as numerous as the quantity of rf package outlines. while the traditional demand for high levels of ruggedness in rf devices assures an intrinsic high tolerance to a wide variety of assembly methods, the high-stress nature of any soldering operation requires careful consideration. users ultimately assume responsibility for developing and q ualifying their soldering processes, and therefore it is strongly recommended to fully evaluate temperature profiles at all steps in the soldering procedure to avoid excessive peak temperatures and ramp rates. when amplifier assemblies require cleaning after soldering operations, the use of a non- reactive cleaning agent is recommended. all residue from reactive flux should be removed according to the flux su pplier's recommendations. if a non-aqueous cleaning method is employed, it must be followed by cleaning with di water to remove all ionic contamination. it is recommended to periodically check the conductivity of the di rinse to insure that levels of ionic contamination are as low as possible. in cases where heavy ionic contamination is present, multiple di rinses in isolated baths should be used. proceed from the most to the least contaminated rinsing system to maximize cleaning effectiveness. in general it is recommended to minimize the us e of flux, to use no-clean flux, or to adopt fluxless soldering techniques. when there is doubt as to the behavior of residual flux or flux levels, consider a two-step solder approach. since the pcb and other components may involve flux, an initial soldering step of the majority of non-critical components can be done, followed by a thorough cleaning. the second solder step, with greatly reduced flux content, can be planned for more critical components such as epoxy sealed rf transistors. an added benefit of a two-step operation is that non-solder thermal interface materials (tims), such as thermal compounds, are not influenced by aggressive flux cleaning. following di rinsing operations, the entire assembly should be baked, as determined by user experimentation, before power is applied. it is suggested to perform this drying at 125 c for 24 hrs, if all components are rated for this condition. a longer bake time is recommended at lower temperatures. refer to figure 2 for some suggestions. oem equipment operating conditions should be specified for operation only in a ?non- condensating? environment. if there is a question of humidity in ambient conditions in power cycling, a heating/drying cycle is recommended before power is applied.
AN3232 exceptional thermal performance potential of the stac package concept doc id 17594 rev 3 7/26 2 exceptional thermal performance potential of the stac package concept rf power transistors are made up of hundreds of thousands of heat generating cells, organized in an ultra-compact geometry at the silicon chip level. the necessity to generate rf power at ever-increasing freq uencies leads directly to the shrinking of silicon geometries to ever-smaller portions of electrical wavelength. the result is unprecedented power density, unmatched by most devices in the semiconductor industry. indeed, such a power density approaches those frequently encountere d in the realm of high-energy physics. the highest priority of the power transistor pack age is efficient evacuation of the incredible thermal flux from the active regions of semi conductor chips to the external environment. great advances made to improve packaging systems and materials have enhanced this effect, including the use of high thermal conduc tivity materials, the reduction of thermal path length, and the improvement of thermal interfaces by way of superior flatness coupled with enhanced tims. a demonstration of the high power density of one device in the stac family is shown in figure 3 by way of infrared imaging. in this example, the junction temperature of the semiconductor chips, dissipating a total of 400 w continuously, is maintained uniformly below the maximum allowable temperature of 200 c, while the case is elevated almost to its maximum of 85 c. figure 3. infrared imaging of a stac package as is the case with many rf power devices, thermal resistance is dominated by the chips themselves, as can be ascertained in figure 3 . in addition, the thermal conductivity of silicon decreases with increasing te mperature, therefore it is common practice to evaluate power transistors near the maximum operating temperatures. taking this into account, the observed thermal resistance, or r thj-c of approximately 0.30 c/w for this stac product, is
exceptional thermal performance potential of the stac package concept AN3232 8/26 doc id 17594 rev 3 approximately 30 % lower than it's ceramic package cousin, the ubiquitous gemini package. this situation affords amplifier designers extreme flexibilit y in terms of trade-offs between power dissipated, output power, power density, and mttf. for example, higher power can be dissipated for a target junction temperatur e, or, on the other hand, increased mttf can be achieved for a target case temperature with equivalent power density. while such flexibility often shifts the burden of cooling to system level, this decision is often the more cost effective solution or easier to manage. alternatively, such a solution could translate into the ability to move an amplifier system from ground level to pole top. in the end analysis, the choice of heatsinking system depends on the specific device and application needs.
AN3232 heatsink selection doc id 17594 rev 3 9/26 3 heatsink selection the critical choice of a heatsinking system dep ends on the specific device and application requirements. the decision resu lts in the total power dissipat ion capability for the amplifier assembly and greatly influences system performance and cost. when the operating conditions of the device are such that the dissipated power is low, a basic thermal core layer without fins may be a ll that is required for maintaining a low case temperature, a high mttf, or adherence to ot her maximum device ratings. examples of applications with low average power diss ipation can include low duty-cycle pulsed amplification or backed-off linear power amplifiers. most often, rf power devices are operated at the highest power levels possible, to extract the most value for the cost. combining the exceptional performanc e of recent silicon improvements, having much higher power efficiency than in previous years, with the thermal performances of stac packages, allows the po ssibility for designers to specify relatively simple systems like low-cost, extruded aluminum heatsinks with fins to provide sufficient cooling. such systems have good thermal and electrical properties for a majority of applications and operating conditions. one benefit of stac packages is to enable designers to ?push the envelope? in terms of power density. first, high thermal flux is managed using a heat spreading copper core layer between the transistor and a high performance heatsink. second, for the most demanding applications, system such as water cooling, heat pipes, and others can be coupled to the first, affording a means of transferring heat very quickly to a more convenient location. for a high performance package such as stac, the preferred heatsink material interposed between the package base and the heatsink is (uns c10100) copper. hereafter this material layer is referred to as the core. based on requirements for typical applications, the thickness range for the core layer is listed in ta bl e 1 . other copper grades and even aluminum may be used for the core layer based on application needs. in these cases, it is advised to adjust core thickness appropriately to control spreading of the heat. table 1. preferred copper core thickness minimum typical maximum 0.12 in (3.0 mm) 0.22 in (5.6 mm) 0.32 in (8.1 mm)
core preparation AN3232 10/26 doc id 17594 rev 3 4 core preparation by design, the stac package family does not require complex core preparation, such as channels, pockets, cavities, etc., assuming a typical pcb thickness is selected for the application. however, because of the intended use of these packages, some aspects of core preparation are appropriate. holes for screws, solder wells, etc., should be slightly countersunk and/or de-burred to achieve the best performance. in soft materials such as copper, the tapping operation can lift material above the mounting surfaces. this may occur on either side of the core layer, so both sides should be inspected. it is sometimes helpful to fully thread test screws in the holes and tighten, to observe if the core material is pushed or pulled above the mounting surfaces. if such a mushroom effect is observed, it is an indication that additional countersinking of the tapped holes is warranted. it is advised to drill and tap through the entire core layer, whenever possible. in the case of boltdown mounting of stac packages, the minimum tapped hole depth should be 0.12 in (3.0 mm). depending on the process used to fabricate the core layer, it is common industry practice to recommend stress relieving the core material, such as an annealing step before (and sometimes after) the heavy machining steps. this should be considered whenever there are a large number of cuts, holes, and other machined features in the core layer. the flatness of the core layer should be inspected after all machining steps to insure that a buildup of stress has not caused it to become warped or otherwise deformed.
AN3232 mounting base surface conditions doc id 17594 rev 3 11/26 5 mounting base surface conditions the mounting base, or the surface of the core to which the backside of the package is mounted, must be flat, clean, and free of tool marks. recommended specifications for the surface conditions are shown in ta bl e 2 . flatness and roughness values can be achieved on the above mentioned materials with standard machining processes, such as milling. improved flatness and lower roughness values reduce both electric al and thermal resistance. table 2. surface conditions flatness roughness, r a 400 in / in (0.4 m/mm) < 30 in (0.8 m)
thermal interface material AN3232 12/26 doc id 17594 rev 3 6 thermal interface material careful consideration must be paid to the actual interface layer between the backside of the package and the mounting base. cleanliness is key: particulates, grease, and oxidation should be removed using standard practices. a thermal interface material (tim) of good thermal conductivity sh ould be used in order to fill any discontinuities between the package and mo unting base surface. the decision of which tim material to use is based on many factors. many types of tims are available with an incredible range of thermal, electrical, and mechanical properties. a few are listed in ta bl e 3 . in all cases, the chosen tim should be no thicker than necessary and applied as evenly as possible. for liquidus compounds, it is easiest to apply it to the backside of the package, keeping in mind that excessive tim thickness results in a higher thermal resistance than using no tim at all. application of pressure displaces liquidus tims in regions of metal-to- metal contact, and fills in any remaining air gaps, thus resulting in excellent electrical and thermal contact. for foils and soldering, it is best to specify an appropriately sized ?preform?, with a thickness of approximately 0.003 in(0.08 mm), and apply it to the core layer or heatsink. in soldering of au plated components which have not been pre-treated by hsd or tinning, enough solder should be used so that the final au content of the multi-eutectic alloy is less than 4 % by weight, to avoid ?gold embrittlement? issues. excessive au content in pb and pb-free alloys can result in a brittle solder joint which degrad es over time with continuous power/temperature cycling. table 3. common tims type description supplier paste or grease wpsii (silicone-free) austerlitz electronics type 340 dow corning type 120(silicone based) wakefield thermal solutions foil or film based indium preform indium solder based pb or pb-free preform various pb or pb-free paste various
AN3232 seating plane doc id 17594 rev 3 13/26 7 seating plane the seating plane refers to the plane determined by the bottom surface of the leads after the package has been mounted. for design purposes, it is the distance between the bottom surface of the package base and the bottom surface of the transistor leads. this important dimension is specified on package outline drawings, and for through-the-board mounting of high power packages, it indicates total depth of the pocket into which the transistor is seated. to determine the depth of this pocket, the total thickness of the pcb, cu traces, solder layers, and the depth of any machined channel is considered. some points to factor into this calculation are shown in figure 4 . figure 4. pocket depth consideration (mm) care should be taken to factor in the thickness of the tim, which is equivalent to increasing the seating plane dimension. along similar lines, if the pcb is fused to the heatsink by means of a bonding film, solder layer, etc., the corresponding thickness of this layer should be factored into the pcb thickness. the leads of the transistor should launch perpendicular to the package body onto the traces of the pcb to reduce mechanical stress to the package and solder joints. in some cases, the pcb fabrication tolerance is such that the leads extend above the plane defined by the top of the pcb; this situation is best handled with a judicious selection of solder pad preform or paste thickness, or by a slight downward bending of the transistor leads [no more than 0.01 in (0.25 mm)]. figure 5. lead bending as with almost all power packages, in no case should the leads be bent higher than the topside of the pcb, unless specific lead-forming techniques are applied, such as those shown in figure 5 . whenever non-coplanarity exists between the bottom of the device leads and the top surface of the pcb, assembly mechanical stresses and cyclic life stresses should be considered. both lead-forming and a pcb pullback, such as that shown in
seating plane AN3232 14/26 doc id 17594 rev 3 figure 6 , are effective methods to reduce shear stress. in applications where there is doubt concerning lead stress, users can consult stmi croelectronics or it's resellers for analysis and advice.
AN3232 printed circuit board (pcb) considerations doc id 17594 rev 3 15/26 8 printed circuit board (pcb) considerations a pocket feature through the pcb, with access to the core layer, is necessary for proper mounting of the package. this pocket may be referred to as the ?package-cut?, or an oversized slot defined on an appropriate routed layer of the pcb stack. one such package- cut design is depicted in figure 6 . in this example, both performance optimization using positioning notches and mechanical stress relief for the leads are achieved. the dimensions for slots should be approximately 0.010 to 0.025 in (0.25 to 0.64 mm) greater than the outside dimensions of the package body. figure 6. package cut and pads layout stac244 and stac265 packages were designed to be compatible with pcbs having dielectric thicknesses in the range of 0.020 to 0.060 in (0.51 to 1.52 mm) - a wide range, covering a large scope of applications. generally, the more the typical pcb thickness specification deviates from the typical seat ing plane dimension, the greater the offset dimensions for the slots. often, the pcb traces are slightly pulled back from the edge of the slot. this ?pullback? technique is useful for situations in which the dimensions of the slot offset are constrained. among other benefits, trace pullbacks provide for reduced stress upon the leads and package body. solder pad layouts for the transistor leads should be designed as large as the circuit topology allows, but it is recommended that pad dimensions be at least the maximum width and the remaining length of the leads (after the above pullbacks are considered). in most cases a border around the leads of at least 0.01 in (0.25 mm) is advised, which allows for a good solder fillet along three si des of each transistor lead.
package attachment to core by means of boltdown method AN3232 16/26 doc id 17594 rev 3 9 package attachment to core by means of boltdown method 9.1 required hardware the recommended fastener system consists of: printed circuit or wiring board (pcb or pwb) core layer, normally copper boltdown stac package choice of tim 2 each of 4-40 unc-2a (or m3) torx, hex, or phillips cap screws (one for each end of the package body) 2 each of spring washers, id=0.150"(3.81 mm) od=0.275"(6.98 mm), t=0.015"(0.38 mm), h=0.025"(0.62mm) means of measuring torque 9.2 considerations the ideal screw-center spacing for stac244b and stac265b packages is 1.1 inch (27.94 mm). this dimension is the same as recommended for legacy "gemini" package outlines such as m244, m252, m265 as well as other familiar equivalents in the industry. regardless of the spacing, the key objective is to insure that long and short centerlines of the package body are centered along and between the screws, respectively. this alignment procedure insures that the clamping forces are correctly balanced, such that the stac clamping design directs pressure down and towards the center of the package body.
AN3232 package attachment to core by means of boltdown method doc id 17594 rev 3 17/26 figure 7. ideal screw-center spacing the boltdown procedure begins with the application of the tim to the back of the package, followed by the insertion of the package into the application board. in the partially exploded view shown in figure 7 , the washers are positioned between the screw head and the bolting surfaces of the package. it is best to start the screws in both tapped holes as demonstrated in figure 8 , continuing in an alternating fashion until finger tightness is achieved. this method insures the package is properly seated and aligned before the final tightening sequence.
package attachment to core by means of boltdown method AN3232 18/26 doc id 17594 rev 3 figure 8. first boltdown mounting steps to further improve the distribution of pressure from the screw head/spring washer combination, an optional flat washer, with an outer diameter no greater than 0.28 in(7.1 mm), may be inserted between the spring washer and the package bolting surfaces. many types of spring washer are available, such as split, conical, belleville, and wave. the choice of spring washer is left to the amplifier designer and choices may vary depending on the application. finally, alternately tighten both screws in steps up to the recommended torque value using a torque driver or equivalent. depending on the choice of tim, the final required screw torque should be adjusted within the range listed in ta b l e 4 . when the above procedure is properly applied, uniform pressure with tolerance for thermal expansion is provided. the mechanical features designed in the stac boltdown package translate the force towards the center of the package at the prescribed screw torque. along with the material set featuring low creep and fatigue resistance, the stac package and the complete hardware system insure that pressure is maintained uniformly over time. table 4. recommended screw torque minimum typical maximum 3.5 in-lb 5.0 in -lb 6.5 in-lb 0.4 n-m 0.6 n-m 0.75 n-m 4 kg-cm 5.8 kg-cm 7.5 kg-cm
AN3232 package attachment to core by means of boltdown method doc id 17594 rev 3 19/26 9.3 procedure summary 1. tighten both fastener systems to each end of the package body to a ?finger-tight? condition, approximately 0.4 in-lb (0.05 n-m, 0.5 kg-cm). 2. use a torque driver or equivalent means to tighten both screws to the recommended torque of 5 in-lbs (0.6 n-m, 5.8 kg-cm).
package attachment to thermal base by means of soldering AN3232 20/26 doc id 17594 rev 3 10 package attachment to thermal base by means of soldering 10.1 hardware printed circuit or wiring board (pcb or pwb) solderable core layer, normally copper stac package (can be flangeless or boltdown version) pb or pb-free solder preform or similar solder paste solder reflow equipment, such as an oven optional mechanical hardware to locate the package 10.2 solder reflow equipment and methods there are many methods for soldering; which method to use is based on factors outside the scope of this application note. for the stac package comprising a material set in use for decades, st feels comfortable recommending a convection reflow oven, preferably with 5 zones plus a cooling strategy. for example, the seho fds ?maxipower? unit depicted in figure 9 , with independent top and bottom heaters and a refrigerated cooling zone, has been used in testing stac packages for reflow soldering and is well-known throughout the industry. figure 9. seho fds ?maxipower? reflow oven an important consideration for reflowing power packages like the stac is that the temperature profile must be adjusted on a case-by-case application basis. no universal profile can account for the large variation in thermal mass between various rf power amplifier (rfpa) assemblies. an rfpa might consist of a relati vely small pcb and thin core layer, which can be soldered with a relatively fast conveyor speed. on the other hand, a large area rfpa pallet, having a thick copper core layer, requires much slower movement through the reflow oven to achieve good soldering. the pcb acts in insulating the top of the core layer from topside heating, therefore a programming balance between top and bottom
AN3232 package attachment to thermal base by means of soldering doc id 17594 rev 3 21/26 heating zones may be required to optimize for uniform temperatures at the interface of the stac package and copper core layer. regardless of the amplifier assembly and choice of soldering method, the industry standard reflow profile recommended in j-std-020d for solder reflow operations is acceptable for stac packages. it is important that this profile, as shown in figure 10 , is respected at the component level. according to table 4-2 of the jedec reference, a max tp of 245 c is advised, but stac packages can survive many reflows at temperatures up to a body temperature of 265 c with no damage. however, such excursions up to this extreme temperature are not recommended because many other board level components may not survive such stressful conditions. figure 10. component level temperature profile note: tp= 20-40 sec, ramp-up = 3 c/sec max, t l = 60-150 sec, ramp-down = 6 c/sec max, t l = 217 c, t smax = 200 c, t smin = 150 c, t s = 60-180 sec, from t 25 c to peak = 8 minutes max, tp = ta b l e 5 . table 5. pb-free process - package classification reflow temperatures (1) 1. tolerance: the device manufacture r/supplier assures process compatib ility up to and including the stated classification temperature (this means peak reflow temperature + 0 c. for example 260 c + 0 c) at the rated msl level. package thickness volume mm 3 < 350 volume mm 3 350-2000 volume mm 3 > 2000 < 1.6 mm 260 + 0 c 260 + 0 c 260 + 0 c 1.6 mm - 2.5 mm 250 + 0 c 245 + 0 c > 2.5 mm 250 + 0 c 245 + 0 c
package attachment to thermal base by means of soldering AN3232 22/26 doc id 17594 rev 3 note: the profiling tolerance is + 0 c, -x c (based on the machine variation capability) regardless of what is required to control the profile process, but at no time does it exceed -5 c. the producer assures pr ocess compatibility at the pe ak reflow temperatures. package volume excludes external terminals (balls, bumps, lands, leads) and/or non- integral heatsinks. the maximum component temperature reached during reflow depends on package thickness and volume. the use of convection reflow processes reduces the thermal gradients between packages. however, thermal gradients due to differences on thermal mass of smd packages may still exist. ultimately, the most stressful aspect of soldering for packaging consisting of plastic or epoxy layers is related to rapid transition between process steps. for this reason, it is recommended to never exceed the ramping rates recommended in j-std-020d at the package level.
AN3232 electrical connection doc id 17594 rev 3 23/26 11 electrical connection leads and/or flanges should be attached to the pcb and/or copper heatsinks using typical sn63pb37 or pb-free solders, in accordance with the supplier's recommendations. however, the following guidelines with respec t to the package should be considered: avoid, as much as possible, the use of flux or flux solutions as it is a potential source of contamination to the device. the leads of the transistor may be tinned prior to assembly on the pcb. this practice is used in situations when it is undesirable to introduce even a small amount of gold into the solder composition, fore stalling the possibility of sold er embrittlement issues. the source of au stems from the lead and/or backside surfaces, which are plated with 40 to 100 in (1 to 2.5 m) of au. the amount of solder to be used depends on the type of solder and the amount of allowable au in the final solder composition. it is desirable to increase the amount of solder when au content is a concern, such as in pb-free soldering applications. it is recommended to use either a solder preform or solder paste having a thickness of 0.001 to 0.010 in (0.03 to 0.3 mm), typically 0.006 in (.15 mm). adjustment of the solder preform or paste thickness may be used advantageously to account for thickness variations in the pcb manufacturing process. in cases where the backside of the flange is soldered to a copper core or heatsink, the package design and previously discussed mechanical mounting procedure provide sufficient downward pressure on the solder preform, resulting in a thin, high-quality bondline after a typical solder reflow procedure. in such cases, solder-wells or a solder- moat around the perimeter of the flange should be considered, to provide a region for excess solder to flow. a solder preform or other metallic foil ma y be used as both a tim and electrical interface between the backside of the package (source) and amplifier ground (normally the core layer or the heatsink) even without soldering. electrically insulative thermal pastes must be applied sufficiently thin, such that the downward pressure is high enough to force metal-to-metal contact over a significant area of the surfaces between the package (source) and amplifier ground.
conclusion AN3232 24/26 doc id 17594 rev 3 12 conclusion this application note provides a set of guidelines to be considered for the proper attachment of stac packages. while these recommendations are intended to address the majority of user applications, the flexibility afforded by this new generation of package technology enables new approaches for amplifier assembly as well as novel system architectures. in the search for constant improvement, st continues to address customer needs by improving the robustness of the stac package line and by releasing additional outlines with more functionality and versatility. for these reasons, it is expected that these guidelines are to be revisited and updated over time. at present, these recommendations are expected to result in reliable mechanical, electrical, and thermal performance. regarding the thermal expectations of stac packages, this application note demonstrates the exceptional performance that can be at tained when utilizing th e solder-down mounting method; this can be viewed as the limiting case for lowest achievable thermal resistance. while the stac package concept embodies highly customizable thermal solutions by means of chip carrier material substitution, the importance of an exceptionally low thermal resistance between the transistor case and the heatsink (r thc-hs ) cannot be overstated. in the case presented, this interface accounts for only 0.025 c/w, roughly half of what is achievable with industry standard flanged packages. in this regard, stac packages afford intrinsic flatness and the highest available ther mal conductivity materials, further enhancing cooling efficiency. even without soldering, judicious selection of tims and respect to this set of guidelines results in r thc-hs values on the order of 0.05 c/w.
AN3232 revision history doc id 17594 rev 3 25/26 13 revision history 27-jul table 6. document revision history date revision changes 03-aug-2010 1 initial release. 08-jun-2011 2 updated figure 7: ideal screw-center spacing and section 9.2: considerations . 31-aug-2011 3 introduction on cover page has been updated.
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